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dram module kmm366f80(8)4cs1 kmm366f80(8)4cs1 edo mode without buffer 8m x 64 dram dimm using 4mx16, 8k & 4k refresh, 3.3v the samsung kmm366f80(8)4cs1 is a 8mx64bits dynamic ram high density memory module. the samsung kmm366f80(8)4cs1 consists of eight cmos 4mx16bits drams in tsop 400mil packages and one 2k eeprom for spd in 8-pin tssop package mounted on a 168-pin glass- epoxy substrate. a 0.1 or 0.22uf decoupling capacitor is mounted on the printed circuit board for each dram. the kmm366f80(8)4cs1 is a dual in-line memory module and is intended for mounting into 168 pin edge connector sockets. general description features performance range speed t rac t cac t rc t hpc -5 50ns 13ns 84ns 20ns -6 60ns 15ns 104ns 25ns pin configurations note : a12 is used for only kmm366f884cs1 (8k ref.) pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 front v ss dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 dq8 v ss dq9 dq10 dq11 dq12 dq13 v cc dq14 dq15 *cb0 *cb1 v ss nc nc v cc w0 cas0 pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 front cas1 ras0 oe0 v ss a0 a2 a4 a6 a8 a10 a12 v cc v cc du v ss oe2 ras2 cas2 cas3 w2 v cc nc nc *cb2 *cb3 v ss dq16 dq17 pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 front dq18 dq19 v cc dq20 nc du nc v ss dq21 dq22 dq23 v ss dq24 dq25 dq26 dq27 v cc dq28 dq29 dq30 dq31 v ss nc nc nc sda scl v cc pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 back v ss dq32 dq33 dq34 dq35 v cc dq36 dq37 dq38 dq39 dq40 v ss dq41 dq42 dq43 dq44 dq45 v cc dq46 dq47 *cb4 *cb5 v ss nc nc v cc du cas4 pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 back cas5 ras1 du v ss a1 a3 a5 a7 a9 a11 *a13 v cc du du v ss du ras3 cas6 cas7 du v cc nc nc *cb6 *cb7 v ss dq48 dq49 pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 back dq50 dq51 v cc dq52 nc du nc v ss dq53 dq54 dq55 v ss dq56 dq57 dq58 dq59 v cc dq60 dq61 dq62 dq63 v ss nc nc sa0 sa1 sa2 v cc pin names * these pins are not used in this module. pin name function a0 - a11 address input (4k ref.) a0 - a12 address input (8k ref.) dq0 - dq63 data in/out w0 , w2 read/write enable oe0 , oe2 output enable ras0 - ras3 row address strobe cas0 - cas7 column address strobe v cc power(+3.3v) v ss ground nc no connection du don t use sda serial address /data i/o scl serial clock sa0 -sa2 address in eeprom *cb0 - cb7 check bit ? part identification ? new jedec standard proposal without buffer ? serial presence detect with eeprom ? extended data out mode operation ? cas -before- ras refresh capability ? ras -only and hidden refresh capability ? lvttl compatible inputs and outputs ? single +3.3v 0.3v power supply ? pcb : height(1000mil), double sided component part number pkg ref. cbr ref. ror ref. kmm366f804cs1 tsop 4k 4k/64ms kmm366f884cs1 tsop 8k 4k/64ms 8k/64ms
dram module kmm366f80(8)4cs1 cas0 functional block diagram v cc vss 0.1 or 0.22uf capacitor under each dram to all drams ras0 w0 oe0 a0-a11(a12) cas1 u0 serial pd sda scl a1 a2 a0 sa1 sa2 sa0 cas2 cas3 u1 ras1 u4 dq0~7 dq8~15 dq16~23 dq24~31 cas4 ras2 w2 oe2 cas5 u2 cas6 cas7 u3 ras3 u6 dq32~39 dq40~47 dq48~55 dq56~63 u5 u7 lcas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 ucas dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 ucas dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 ucas dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 ucas dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 ucas dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 ucas dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 ucas dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 lcas dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 ucas dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 note : a12 is used for only kmm366f884cs1 (8k ref.)
dram module kmm366f80(8)4cs1 i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one edo mode cycle time, t hpc . * note : absolute maximum ratings * * permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for in tended periods may affect device reliability. item symbol rating unit voltage on any pin relative v ss voltage on v cc supply relative to v ss storage temperature power dissipation short circuit output current v in , v out v cc t stg p d i os -0.5 to +4.6 -0.5 to +4.6 -55 to +150 8 50 v v c w ma recommended operating conditions (voltage referenced to v ss , t a = 0 to 70 c) *1 : v cc +1.3v at pulse width 15ns which is measured at v cc . *2 : -1.3v at pulse width 15ns which is measured at v ss . item symbol min typ max unit supply voltage ground input high voltage input low voltage v cc v ss v ih v il 3.0 0 2.0 -0.3 *2 3.3 0 - - 3.6 0 v cc +0.3 *1 0.8 v v v v dc and operating characteristics (recommended operating conditions unless otherwise noted) i cc1 i cc2 i cc3 i cc4 i cc5 i cc6 i( il) i( ol) v oh v ol symbol speed kmm366f884cs1 kmm366f804cs1 unit min max min max i cc1 -5 -6 - - 324 284 - - 484 444 ma ma i cc2 don t care - 8 - 8 ma i cc3 -5 -6 - - 324 284 - - 484 444 ma ma i cc4 -5 -6 - - 364 324 - - 364 324 ma ma i cc5 don t care - 4 - 4 ma i cc6 -5 -6 - - 484 444 - - 484 444 ma ma i i(l) i o(l) don t care -10 -10 10 10 -10 -10 10 10 ua ua v oh v ol don t care 2.4 - - 0.4 2.4 - - 0.4 v v : operating current * ( ras , cas , address cycling @ t rc =min) : standby current ( ras = cas = w =v ih ) : ras only refresh current * ( cas =v ih , ras cycling @ t rc =min) : extended data out mode current * ( ras =v il , cas cycling : t hpc =min) : standby current ( ras = cas = w =v cc -0.2v) : cas -before- ras refresh current * ( ras and cas cycling @ t rc =min) : input leakage current (any input 0 v in v cc +0.3v, all other pins not under test=0 v) : output leakage current(data out is disabled, 0v v out v cc ) : output high voltage level (i oh = -2ma) : output low voltage level (i ol = 2ma)
dram module kmm366f80(8)4cs1 capacitance (t a = 25 c, v cc =3.3v, f = 1mhz) item symbol min max unit input capacitance[a0-a12] input capacitance[ w0 , w2 , oe0 , oe2 ] input capacitance[ ras0 - ras3 ] input capacitance[ cas0 - cas7 ] input/output capacitance[dq0-dq63] c in1 c in2 c in3 c in4 cdq - - - - - 50 38 24 24 24 pf pf pf pf pf ac characteristics (0 c t a 70 c, v cc =3.3v 0.3v. see notes 1,2.) test condition : v ih /v il =2.2/0.7v, v oh /v ol =2.0/0.8v, output loading c l =100pf parameter symbol -5 -6 unit note min max min max random read or write cycle time t rc 84 104 ns read-modify-write cycle time t rwc 128 153 ns access time from ras t rac 50 60 ns 3,4,9 access time from cas t cac 13 15 ns 3,4,5 access time from column address t aa 25 30 ns 3,9 cas to output in low-z t clz 3 3 ns 3 oe to output in low-z t olz 3 3 ns 3 output buffer turn-off delay from cas t cez 3 13 3 13 ns 6,12 transition time(rise and fall) t t 1 50 1 50 ns 2 ras precharge time t rp 30 40 ns ras pulse width t ras 50 10k 60 10k ns ras hold time t rsh 8 10 ns cas hold time t csh 38 40 ns cas pulse width t cas 8 10k 10 10k ns ras to cas delay time t rcd 17 37 20 45 ns 4 ras to column address delay time t rad 12 25 15 30 ns 9 cas to ras precharge time t crp 5 5 ns row address set-up time t asr 0 0 ns row address hold time t rah 7 10 ns column address set-up time t asc 0 0 ns 13 column address hold time t cah 7 10 ns 13 column address to ras lead time t ral 25 30 ns read command set-up time t rcs 0 0 ns read command hold referenced to cas t rch 0 0 ns 8 read command hold referenced to ras t rrh 0 0 ns 8 write command hold time t wch 7 10 ns write command pulse width t wp 7 10 ns write command to ras lead time t rwl 8 10 ns write command to cas lead time t cwl 7 10 ns 16 data set-up time t ds 0 0 ns data hold time t dh 7 10 ns refresh period (4k & 8k ref.) t ref 64 64 ms write command set-up time t wcs 0 0 ns 7 cas to w delay time t cwd 33 38 ns 7, 15 ras to w delay time t rwd 70 84 ns 7
dram module kmm366f80(8)4cs1 ac characteristics (0 c t a 70 c, v cc =3.3v 0.3v. see notes 1,2.) test condition : v ih /v il =2.2/0.7v, v oh /v ol =2.0/0.8v, output loading c l =100pf parameter symbol -5 -6 unit note min max min max column address to w delay time t awd 45 53 ns 7 cas precharge to w delay time t cpwd 47 58 ns cas setup time ( cas -before- ras refresh) t csr 5 5 ns 17 cas hold time ( cas -before- ras refresh) t chr 10 10 ns ras to cas precharge time t rpc 5 5 ns access time from cas precharge t cpa 28 35 ns 3 hyper page mode cycle time t hpc 20 25 ns 10 hyper page mode read-modify write cycle time t hprwc 67 73 ns 10 cas precharge time (hyper page cycle) t cp 7 10 ns 14 ras pulse width (hyper page cycle) t rasp 50 200k 60 200k ns ras hold time from cas precharge t rhcp 30 35 ns oe access time t oea 13 15 ns oe to data delay t oed 10 13 ns output buffer turn off delay time from oe t oez 3 13 3 13 ns 6 oe command hold time t oeh 5 5 ns output data hold time t doh 5 5 ns output buffer turn off delay from ras t rez 3 13 3 13 ns 6,12 output buffer turn off delay from w t wez 3 13 3 13 ns 6 w to data delay t wed 15 15 ns oe to cas hold time t och 5 5 ns cas hold time to oe t cho 5 5 ns oe precharge time t oep 5 5 ns w pulse width (hyper page cycle) t wpe 5 5 ns
dram module kmm366f80(8)4cs1 notes an initial pause of 200us is required after power-up followed by any 8 ras -only or cas -before- ras refresh cycles before proper device operation is achieved. input voltage levels are v ih /v il . v ih (min) and v il (max) are ref- erence levels for measuring timing of input signals. transi- tion times are measured between v ih (min) and v il (max) and are assumed to be 5ns for all inputs. measured with a load equivalent to 1 ttl loads and 100pf. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes that t rcd 3 t rcd (max). this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . t wcs , t rwd , t cwd and t awd are non-restrictive operating parameter. they are inclueded in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min) and t awd 3 t awd (min), then the cycle is a read-write cycle and the data output will contain the data read from the selected address. if neither of the above conti- tions are satisfied, the condition of the data out is indeterni- mated. either t rch or t rrh must be satisfied for a read cycle. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . t asc 3 6ns, assume t t = 2.0ns. for all of the refresh mode except distributed cas -before ras refresh, 4096 cycle of burst refresh must be executed within 16ms before and after self-refresh in order to meet refresh specification. if ras goes to high before cas high going, the open circuit condtion of the output is achieved by cas high going. if cas goes to high before ras high going, the open circuit cond- tion of the output is achieved by ras high going. t asc , t cah are referenced to the earlier cas falling edge. t cp is specified from the last cas rising edge in the previous cycle to the first cas falling edge in the next cycle. t cwd is referenced to the later cas falling edge at word read- modify-write cycle. t cwl is specified from w falling edge to the earlier cas rising edge. t csr is referenced to earlier cas falling low before ras tran- sition low. 1. 2. 3. 4. 5. 6. 7. 9. 10. 11. 12. 13. 14. 15. 16. 8. 17.
dram module kmm366f80(8)4cs1 ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t asr t rah t asc t cah t crp t aa t oea t clz t rac open t rch don t care undefined t rad t rrh data-out t rez t rcs read cycle t oez t cez t wez dq t olz t cac
dram module kmm366f80(8)4cs1 t wcs note : d out = open write cycle ( early write ) ras v ih - v il - v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp don t care undefined t wch t wp cas t rwl t cwl t ds t dh data-in dq
dram module kmm366f80(8)4cs1 note : d out = open write cycle ( oe controlled write ) ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp t wp don t care undefined cas v ih - v il - t rwl t cwl t dh t oeh t oed data-in t ds
dram module kmm366f80(8)4cs1 read - modify - write cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq row addr t ras t rwc t rp t rsh t rcd t cas t csh t rad t asr t rah t asc t cah t crp valid t wp don t care t rwl t cwl t oez t oea t oed t awd t cwd t rwd data-out undefined valid data-in t rac t aa t cac t clz t ds t dh column address t olz
dram module kmm366f80(8)4cs1 t doh hyper page read cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp t rcd t asr t crp don t care undefined v oh - v ol - dq t oep column address t cas t cas t cas t cas t cp t cp t cp t hpc t hpc t hpc t rhcp t csh t rad t rah t asc t cah t cah t cah t asc t cah t rcs t aa t rch t asc column address column addr valid data-out t oez t oea t oep t aa t cac t oea t aa t cpa t cac t cpa valid data-out valid data-out t oez t clz t rac t oea t olz t cac t rrh t cho t rez t oez t cac t och t cpa t cac valid data-out ? t asc t aa
dram module kmm366f80(8)4cs1 ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr. t rasp t rp t rcd t asr t crp don t care hyper page write cycle ( early write ) undefined v ih - v il - dq t rhcp t rad t rah t cah t cah t asc t cah t asc valid data-in t ds ? column address column address t cas t cp t cas t cp t cas t rsh ? t csh t asc ? ? t wp t wcs t wch t wp t wcs t wch t wp t wcs t wch ? ? ? valid data-in valid data-in ? ? t dh t ds t dh t ds t dh t cwl t cwl t cwl t rwl note : d out = open t hpc t hpc
dram module kmm366f80(8)4cs1 don t care hyper page read-modify-write cycle undefined ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - row addr t csh t rasp t rp t asr t rah t rcd t cp t rad t cah t wp t dh col. addr col. addr t cas t cas t crp t asc t cah t ral t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t cwl t rac t oea t clz t oez t cpwd t oed t asc t clz t oea t cac t aa t dh t oed t rwl t crp t ds t oez valid data-out valid data-in valid data-out valid data-in t ds dq t rsh t olz t olz t hprwc t cac t aa
dram module kmm366f80(8)4cs1 hyper page read and write mixed cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp don t care undefined v i/oh - v i/ol - dq t wez t cp t cp t hpc t hpc t hpc t rad t rah t asc t cah t cah t cah t asc t cah t rch t rcs t rcs t rch t asc column address col. addr valid data-out t rez t aa t wcs valid data-out valid data-out valid data-in t rac col. addr t cas t asr t cas t cas t cas t asc t cp t rch t wch t wpe t clz t cpa t wed t aa t wez t ds t dh t cac t oea read( t cac ) read( t cpa ) write read( t aa )
dram module kmm366f80(8)4cs1 don t care ras - only refresh cycle* note : w , oe , d in = don t care undefined d out = open ras v ih - v il - cas v ih - v il - a v ih - v il - row addr t rc t rp t asr t crp t ras t rah t rpc t crp open cas - before - ras refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rc t rp t ras t rpc t cp t rpc t csr t chr t cez v oh - v ol - dq t wrp t wrh w v ih - v il - t rp * in ras -only refresh cycle of 64mb a-dile & b-die, when cas signal transits from low to high, the valid data may be cut off.
dram module kmm366f80(8)4cs1 hidden refresh cycle ( read ) t oez data-out t rp ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - row address t ras t rc t chr t rcd t rsh t rad t asr t rah t asc t crp don t care undefined v oh - v ol - dq t wrh t rrh column address t oea t ras t rc t cah t rcs t aa t rac t clz t cac t cez open t rp t wez t rez t olz t wrp
dram module kmm366f80(8)4cs1 t crp t wcs t rp ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - row address t ras t rc t rad t asr t rah t asc don t care hidden refresh cycle ( write ) undefined cas v ih - v il - v ih - v il - dq t rsh t rcd t wrh column address t ras t rc t chr t cah t wrp t ds note : d out = open t wp t wch data-in t dh t rp
dram module kmm366f80(8)4cs1 cas -before- ras refresh counter test cycle ras v ih - v il - cas v ih - v il - a v ih - v il - column address t ras t rsh t chr t ral t csr t cpt t rp t cas t asc t cah read cycle v oh - v ol - data-out dq t rez t clz write cycle v ih - v il - data-in dq t dh t ds w v ih - v il - t wp t cwd t cwl t rwl read-modify-write t awd v ih - v il - oe t oea t aa t cac t ds t dh valid data-out v i/oh - v i/ol - dq don t care undefined v ih - v il - oe t oea t oez oe v ih - v il - t rcs t clz t oez t oed t wrp t wrh t rrh t rch t rcs t cac t aa v ih - v il - w t wrp t wrh t wcs t wch t cwl v ih - v il - w t wp t rwl t wrp t wrh valid data-in note : this timing diagram is applied to all devices besides 64m dram based modules. t cez t wez
dram module kmm366f80(8)4cs1 open cas - before - ras self refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rps t rass t rpc t cp t rpc t csr t cez v oh - v ol - dq t rp don t care undefined t chs t wrp t wrh w v ih - v il - open test mode in cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rp t rc t rpc t cp t rpc t csr t cez v oh - v ol - dq t wts t wth w v ih - v il - t chr t rp t ras
dram module kmm366f80(8)4cs1 package dimensions units : inches (millimeters) 0.050 0.039 .002 0.010max (0.250 max) 0.150 max (3.81 max ) 0.050 0.0039 tolerances : .005(.13) unless otherwise specified the used device is 4mx16 dram with edo mode, tsop ii dram part no. : kmm366f884cs1 - km416v4004cs (1.270 0.10) (1.000 . 050) (1.270 ) 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) detail c 0.250 (6.350 ) detail a 0.1230 .0050 (3.125 .125) 0.250 (6.350 ) detail b 0.1230 .0050 (3.125 .125) 0.079 .0040 (2.000 .100) 0.079 .0040 (2.000 .100) 5.250 5.014 r 0.079 (r 2.000) 0.250 (6.350) 1.450 (36.830) 2.150 (54.61) 0.350 0 . 1 0 0 m i n ( 2 . 5 4 0 m i n ) 0 . 7 0 0 ( 1 7 . 7 8 0 ) .118dia .004 (3.000dia .100) (8.890) a b c 0.250 (6.350) .450 (11.430) 4.550 (115.57) 0.157 0.004 (4.000 0.100 ) 0.054 (1.372) (127.350) (133.350) 1 . 0 0 ( 2 5 . 4 0 ) 0.118 (3.000) 0 . 1 1 8 ( 3 . 0 0 0 ) ( front view ) ( back view ) kmm366f804cs1 - km416v4104cs

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